{"type":"img","src":"//cdn.quv.kr/rpgnmrji6/up/5ea26f8acda5d_1920.png","height":63}
  • Company
  • Product
  • Contact
  • {"google":[],"custom":["Noto Sans KR"]}
    ×
     
     
    섹션 설정
    {"type":"img","src":"//cdn.quv.kr/rpgnmrji6/up/5efd582ad7aad_1920.png","height":"22"}
  • Home
  • Company
  • Product
  • Contact
  • PRODUCTS

    GaN Product

    GaN Substrates (Si-doped)

    2 inch Free-Standing

    Gallium Nitride Substrates (Si-doped)


    D-GaNCN-C50
    Resistivity :< 0.05 Ω·cm for N-type (Si-doped)
    Polishing :Ga-face Polishing

    N-face Polishing

    Double side Polishing
    Grade :S-1 / S-2 / A-1 / A-2 / B / C


    Detail

    Specification


    ItemExcellent level (S-1)Excellent level (S-2)Production level (A-1)Production level (A-2)Research level (B)Dummy level (C)
    Dimension⌀ 50.8 ± 1 mm
    Thickness350 ± 25 μm
    Dislocation Density< 9.9x10⁵ cmˉ²< 3x10⁶ cmˉ²< 9.9x10⁵ cmˉ²< 3x10⁶ cmˉ²< 3x10⁶ cmˉ²
    OrientationC-Plane (0001) off angle toward M-Axis  0.35 ± 0.15º (5 points)C-Plane (0001) off angle toward M-Axis  0.35 ± 0.15º (3 points*)
    Orientation Flat(1-100) ± 0.5º, 16.0 ± 1.0 mm
    Secondary Orientation Flat(11-20) ± 3º, 8.0 ± 1.0 mm
    TTV≤ 15 μm
    BOW≤ 20 μm≤ 40 μm
    Resistivity (300K)< 0.05 Ω·cm for N-type (Si-doped)
    Ga face            surface roughness< 0.2nm (polished); or < 0.3nm (polished and surface treatment for epitaxy)
    N  face              surface roughness0.5 ~1.5 μm   option: 1~3 nm (fine ground); < 0.2 nm (polished)
    PackagePackaged in a cleanroom in single wafer container
    Useable area**> 90%> 80%> 70%
    Macro defect density (hole)0 cm< 0.3 cmˉ²< 1 cmˉ²
    Max size of    macro defects
    < 700 μm< 2000 μm< 4000 μm

       * 3 points: the miscut angles of positions (2, 4, 5) are 0.35 ± 0.15°  (Refer to above drawing)

       ** Useable area: edge and macro defects exclusion


    ItemS-1S-2A-1A-2BC
    Dimension⌀ 50.8 ± 1 mm
    Thickness350 ± 25 μm
    Dislocation Density< 9.9 x 10⁵ cmˉ²< 3 x 10⁶ cmˉ²< 9.9 x 10⁵ cmˉ²< 3 x 10⁶ cmˉ²< 3 x 10⁶ cmˉ²
    OrientationC-Plane (0001) off angle toward M-Axis  0.35 ± 0.15º (5 points)C-Plane (0001) off angle toward M-Axis  0.35 ± 0.15º (3 points*)
    Orientation Flat(1-100) ± 0.5º, 16.0 ± 1.0 mm
    Secondary Orientation Flat(11-20) ± 3º, 8.0 ± 1.0 mm
    TTV≤ 15 μm
    BOW≤ 20 μm≤ 40 μm
    Resistivity (300K)< 0.05 Ω·cm for N-type (Si-doped)
    Ga face surface roughness< 0.2nm (polished); or < 0.3nm (polished and surface treatment for epitaxy)
    N  face surface roughness0.5 ~1.5 μm   option: 1~3 nm (fine ground); < 0.2 nm (polished)
    PackagePackaged in a cleanroom in single wafer container
    Useable area**> 90%> 80%> 70%
    Macro defect density (hole)0 cm< 0.3 cmˉ²< 1 cmˉ²
    Max size of macro defects
    < 700 μm< 2000 μm< 4000 μm

       * 3 points: the miscut angles of positions (2, 4, 5) are 0.35 ± 0.15°  (Refer to above drawing)

       ** Useable area: edge and macro defects exclusion


       - S-1, S-2 : Excellent level

       - A-1, A-2 : Production level

       - B : Research level

       - C : Dummy level

    {"google":["Roboto","Noto Sans"],"custom":["Noto Sans KR"]}
    {"google":["Roboto"],"custom":["Noto Sans KR"]}
    {"google":[],"custom":["Noto Sans KR"]}