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    SiC Wafer

    SiC Substrates (Dummy)

    Dummy grade

    Silicon carbide Substrates


    SiC Dummy wafer
    Dimension :4": 100 ± 0.5 mm
    6": 150 ± 0.2 mm
    Thickness :N: 350 ± 25 ㎛
    Si: 500 ± 25 ㎛
    TTV :≤ 20 ㎛
    BOW :-45 ~ 45 ㎛
    Micropipe Density4": ≤ 10 cm-²
    6": ≤ 15 cm-²


    Detail

    Specification

    Item


    Dimension100 ± 0.5 mm150 ± 0.2 mm
    Thickness 350 ± 25 ㎛ (N type)   /   500 ± 25 ㎛ (SI type)
    OrientationOff axis: 0.4º toward <1120> ± 0.15º (N type)
    On axis: <0001> ± 0.2º (SI type)
    Micropipe Density≤ 10 cm-²≤ 15 cm-²
    Resistivity0.015 ~ 0.025 Ω·cm (N type)
    > 1E9 Ω·cm (SI type)
    Primary Flat(1-100) ± 5.0º
    Primary Flat Length32.5 mm ± 1.5 mm47.5 mm ± 1.5 mm
    TTV(Total Thickness Variation)≤ 20 ㎛
    BOW-45 ~ 45 ㎛
    Warp≤ 50 ㎛
    Surface FinishSi-face CMP
    Back FinishC-face CMP
    RoughnessPolish Ra ≤ 0.2 nm
    CMP Ra ≤ 0.2 nm
    Polytype Areas≤ 30 %
    Edge Exclusion2mm
    PackageMulti-wafer cassrtte

    Item


    Dimension⌀ 50.8 ± 1 mm
    Thickness350 ± 25 ㎛
    Usable Surface Area> 90%
    OrientationC-Plane (0001) off angle toward M-Axis 0.35º ± 0.15º
    Orientation Flat(1-100) ± 0.5º, 16.0 ± 1.0 mm
    Secondary Orientation Flat(11-20) ± 3º, 8.0 ± 1.0 mm
    TTV(Total Thickness Variation)≤ 15 ㎛
    BOW≤ 20 ㎛
    Conduction TypeN-typeN-typeSemi-Insulating
    Resistivity (300K)< 0.1 Ω·cm< 0.05 Ω·cm> 10⁶ Ω·cm
    Dislocation DensityFrom 1 x 10⁵ to 3 x 10⁶ cmˉ² (GB/T32282-2015)
    PolishingFront surface: Ra < 0.2nm (polished); or < 0.3nm (polished and surface treatment for epitaxy)
    Back surface: 0.5~1.5㎛; option: 1~3 nm (fine ground); < 0.2 nm (polished)
    PackagePackaged in a class 100 clean room environment, in single container, under a nitrogen atmosphere.

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